On May 25, He Tingbo, Director of Huawei’s Board of Directors and President of HiSilicon, delivered a keynote speech at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai, officially introducing what she termed the “Tao (τ) Law.” This law replaces the traditional “geometric miniaturization” underpinning Moore’s Law with “temporal miniaturization,” while its core technical approach is “LogicFolding.” By vertically stacking planar circuits, this method reduces signal propagation delays and boosts transistor density. It shares similarities with 3D packaging strategies adopted by Intel’s Foveros and AMD’s V-Cache, yet Huawei has managed to implement it independently without relying on EUV lithography machines. He revealed that over the past six years, Huawei has secretly designed and mass-produced 381 chips based on this principle; these efforts were spearheaded by the “Moye” R&D team she established after U.S. sanctions were imposed in 2019. On May 27, Zheng Jun, CTO of Huawei’s Financial Systems Division, further confirmed at the Phoenix Bay Area Finance Forum in Shenzhen that chips developed under the Tao Law are already being used in the upcoming Mate 90 series, noting their manufacturing performance matches industry standards for 3nm processes.
According to currently available performance metrics, the Kirin 2026 chip powering the Mate 90 (set to launch this autumn) boasts a transistor density of 238 million transistors per square millimeter—a 53.5% improvement over the Kirin 9030 Pro. In theory, this figure aligns with Intel’s 18A process and comes close to TSMC’s initial 3nm capabilities. Additionally, its P-core energy efficiency rose by 41%, while peak clock speeds climbed 12.7% to reach 3.1 GHz. The chip was manufactured by SMIC using DUV lithography tools. Analysts from CITIC Construction Investment had earlier predicted test results would “far exceed expectations, outperform Apple’s A18 chip, and match TSMC’s 3nm standards.” Per Huawei’s roadmap tied to the Tao Law, the company aims to achieve a transistor density exceeding 400 million transistors per square millimeter and clock speeds up to 5.0 GHz by 2031—levels comparable to future 1.4nm fabrication technologies. Industry experts point out that while LogicFolding itself isn’t a novel concept, Huawei’s ability to independently scale it via DUV equipment despite stringent sanctions holds considerable strategic value. Future applications may extend to Ascend AI chips and data center clusters, potentially replacing NVIDIA products currently facing restrictions in China.